Modular memory structure having adaptable redundancy circuitry

ABSTRACT

The invention provides a modular memory structure having adaptable redundancy circuitry, which can repair different types of defects using an addressing line and an enabled line, thereby increasing the yield of the memory device. The modular memory structure having adaptable redundancy circuitry includes: a plurality of main memory blocks to store data; a plurality of redundancy memory blocks to replace the defective memory blocks; a plurality of fuse sets to generate replacement signals by programming the plurality of fuse sets to replace the defect memory positions on the main memory blocks with the corresponding redundancy memory blocks.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a memory structure, and particularly toa modular memory structure having adaptable redundancy circuitry, whichuses an enabled line to reduce the fuses required by a programmingredundancy circuit and determines the optimized replacement range ofdefective memory to avoid memory resource waste during the earlydevelopment phase.

[0003] 2. Description of the Related Art

[0004] In a semiconductor memory device, for example, in a dynamicrandom access memory (DRAM) or a static random access memory (SRAM)module, redundancy circuitry is widely used. FIG. 1 is a block diagramof a typical memory block, including redundancy circuitry. As shown inFIG. 1, during the verification of each and every cell on the chipbefore shipping, in the event of data stored into the memory array 16through the port 12 and the interface 14 encountering defective cells inthe memory array 16, redundancy cells 18 are commonly used to replacedefective cells produced by the manufacturing process, therebyincreasing the yield. Following the increment of memory density, ahierarchical decoding (not shown) scheme, e.g. top, middle, and bottomaddressing, is employed in order to further increase the operating speedand reduce the switching power of decoding operation in DRAM and SRAM.Redundancy replacement is activated where a single row of memory cellsor column of memory cells with defects is replaced with a redundancy rowor column 18 by making the fuses connect or blow, i.e., programming, tomap failure addresses (not shown). However, the number of fuses becomesprohibitively large for this conventional redundancy scheme,particularly in high-density memory, in which a lot of room is consumedby thousands of fuses, so that normal memory cells are compressed into alimited space and the implementation of the circuitry becomes overlycomplicated.

SUMMARY OF THE INVENTION

[0005] Therefore, an object of the invention is to provide a modularmemory structure having adaptable redundancy circuitry, which can repairdifferent types of defects to increase the yield of the memory device.

[0006] A further object of the invention is to provide a modular memorystructure having adaptable redundancy circuitry, which uses anaddressing line and an enabled line to reduce the required fuse sets andavoid memory resource waste.

[0007] To realize the above and other objects, the invention provides amodular memory structure having adaptable redundancy circuitry, whichcan repair different types of defects by using an addressing line and anenabled line, thereby increasing the yield of the memory device. Themodular memory structure having adaptable redundancy circuitry includes:a plurality of main memory blocks for storing data; a plurality ofredundancy memory blocks for replacing the defect memory blocks; aplurality of fuse sets to generate replacement signals by programmingthe plurality of fuse sets to replace the defect memory positions on themain memory blocks with the corresponding redundancy memory blocks. Thereplacement signals include an MAT replacement signal, a memory sectorreplacement signal, and a memory row and column replacement signal.Thus, the optimized replacement range is defined by the signals with thesizes of MAT, sector, and row or column.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The invention will become apparent by referring to the followingdetailed description of a preferred embodiment with reference to theaccompanying drawings, wherein:

[0009]FIG. 1 is a block diagram of a typical memory including redundancycircuitry;

[0010]FIG. 2 is a block diagram of a modular memory structure withadaptable redundancy circuitry of the invention; and

[0011]FIG. 3 is a schematic diagram of an adaptable redundancy circuitryof the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0012]FIG. 2 is a block diagram of a modular memory structure 2 withadaptable redundancy circuitry of the invention. In FIG. 2, thestructure includes main memory blocks 21, 23, 25, and 27 for storingdata; redundancy memory blocks 20, 22, 24, 26, 28, and 29 for replacingthe defect positions on the main memory blocks 21, 23, 25, and 27; andfuse sets Fuse₁₃ set 0, Fuse₁₃ set 1, Fuse₁₃ set 2, and Fuse₁₃ set 3 forchoosing the replacement sizes. The replacement sizes include aredundancy cell, a column or a row, a sector, and an MAT. As shown inFIG. 2, the implementation of one main memory with respect to oneredundancy memory plus two additional redundancy memory blocks forms thebody of the memory module 2. For example, every four sectors form an MATand two MATs are arranged in a line. Thus, a redundancy memory line isinterlaced with a main memory line from line 20 to line 27. In addition,two additional redundancy memory blocks 28, 29 follow to form the memorystructure 2 as shown in FIG. 2. Moreover, the memory module 2 iselectrically connected to fuse sets Fuse₁₃ set 0, Fuse₁₃ set 1, Fuse₁₃set 2, and Fuse₁₃ set 3 to complete the implementation. Fuse_set 0 iselectrically connected to the redundancy memory line 20 and the lefthalf of the redundancy memory line 28. Fuse₁₃ set 1 is electricallyconnected to the redundancy memory line 22 and the left half of theredundancy memory line 29. Fuse₁₃ set 2 is electrically connected to theredundancy memory line 24 and the right half of the redundancy memoryline 28. Fuse₁₃ set 3 is electrically connected to the redundancy memoryline 26 and the right half of the redundancy memory line 29. Theadaptable redundancy circuitry is further described as follows.

[0013]FIG. 3 is a schematic diagram of an adaptable redundancy circuitryof the invention. In FIG. 3, the circuitry includes a plurality offuse-added elements FA0-FA8; a plurality of enable fuse elements FENT,FENM, and FENB; a replacement signal generation circuitry 31. As shownin FIG. 3, defect addresses A0-A8 are respectively input to fuse-addedelements FA0-FA8 so as to have the programming function. A column or rowis decoded by the bottom hierarchy addresses A0-A2 through thefuse-added elements FA0-FA2. The outputs of the elements FA0-FA2 areinput to the NAND gate NAND1 of the replacement signal generationcircuitry 31. A sector is decoded by the middle hierarchy addressesA3-A5 through the fuse-added elements FA3-FA5. The outputs of theelements FA3-FA5 are input to the NAND gate NAND2 of the replacementsignal generation circuitry 31. A MAT is decoded by the top hierarchyaddresses A6-A8 through the fuse-added elements FA6-FA8. The outputs ofthe elements FA6-FA8 are input to the NAND gate NAND3 of the replacementsignal generation circuitry 31. In this example, each fuse-added elementhas a distance of 5 μm. A fuse set enable signal FUSET EN isconcurrently input to the enable fuse elements FENT, FENM, FENB to beprogrammed, respectively, so as to generate the corresponding enablesignals TOP₁₃ EN, MID₁₃ EN, and BOT₁₃ EN respectively input to thereplacement signal generation circuitry 31. The replacement signalgeneration circuitry 31 further includes NAND gates NAND1-NAND6, NORgates NOR1 and NOR2, and an inverter NOT. The NAND gate NAND1 receivesthe output signal from the fuse-added elements FA0-FA2 and generates anoutput signal to the NOR gate NOR1. The NAND gate NAND2 receives theoutput signal from the fuse-added elements FA3-FA5 and generates anoutput signal to the NOR gates NOR1 and NOR2. The NAND gate NAND3receives the output signal from the fuse-added elements FA6-FA8 andgenerates a signal N3 to the NOR gate NOR1, NOR2, and the inverter NOT.The NOR gate NOR1 receives the output signal from the NAND gates NAND1,NAND2, and NAND3 and generates an output signal to the NAND gate NAND4.The NOR gate NOR2 receives the output signal from the NAND gates NAND2and NAND3 and generates an output signal to the NAND gate NAND5. Theinverter NOT receives an output signal from the NAND gate NAND3 andgenerates an inverted phase output signal to the NAND gate NAND6. TheNAND gate NAND4 receives signal BOT₁₃ EN and the output of the NOR gateNOR1 to generate the replacement signal BOTRED₁₃ HIT to determine thedefect range replaced with a column or a row. The NAND gate NAND5receives signal MID₁₃ EN and the output of the NOR gate NOR2 to generatethe replacement signal MIDRED₁₃ HIT to determine the defect rangereplaced with a sector. The NAND gate NAND6 receives signal TOP₁₃ EN andthe output of the inverter NOT to generate the replacement signalTOPRED₁₃ HIT to determine the defect range replaced with an MAT. In sucha structure, the replacement signals BOTRED₁₃ HIT, MIDRED₁₃ HIT andTOPRED₁₃ HIT can indicate a replacement size of the defect memory andreplace it with an optimized range by means of the structure of FIG. 2,thereby reducing the required fuses and avoiding wasted space.

[0014] Although the invention has been described in its preferredembodiment, it is not intended to limit the invention to the preciseembodiment disclosed herein. Those who are skilled in this technologycan still make various alterations and modifications without departingfrom the scope and spirit of this invention. Therefore, the scope of theinvention shall be defined and protected by the following claims andtheir equivalents.

What is claimed is:
 1. A modular memory structure having adaptableredundancy circuitry, comprising: a plurality of main memory to storedata; a plurality of redundancy memory to replace the defective memoryin the plurality of main memory; a plurality of fuse sets to beprogrammed to generate replacement signals for the replacement of thedefect memory positions on the main memory blocks with the correspondingredundancy memory blocks.
 2. The modular memory structure of claim 1,wherein the replacement signals comprise an MAT replacement signal, asector replacement signal and a line replacement signal.
 3. The modularmemory structure of claim 2, wherein the line replacement signal is acolumn replacement signal.
 4. The modular memory structure of claim 2,wherein the line replacement signal is a row replacement signal.
 5. Themodular memory structure of claim 1, wherein the fuse sets furthercomprise: a plurality of fuse-added elements to be programmed accordingto a fuse set enable signal input externally to generate the enablesignals to enable the respective defect memory replacement ranges; andreplacement generation circuitry to receive and decode the output of theplurality of fuse-added elements and the enable signals of the pluralityof enable fuse elements to determine a replacement signal for thereplacement range of defect memory with the redundancy memory.
 6. Themodular memory structure of claim 5, wherein the defect memoryreplacement ranges comprise a bit replacement, a line replacement, asector replacement and an MAT replacement.
 7. The modular memorystructure of claim 5, wherein the enable signals comprise an MAT enablesignal, a sector enable signal and a line enable signal.
 8. The modularmemory structure of claim 7, wherein the line enable signal is a columnenable signal.
 9. The modular memory structure of claim 7, wherein theline enable signal is a row enable signal. 10.The modular memorystructure of claim 5, wherein the replacement signals comprise an MATreplacement signal, a sector replacement signal and a line replacementsignal. 11.The modular memory structure of claim 10, wherein the linereplacement signal is a column enable signal. 12.The modular memorystructure of claim 10, wherein the line replacement signal is a rowenable signal.
 13. An adaptable redundancy circuitry having a pluralityof fuse sets, fit to be implemented into the modular memory structurementioned above, the circuitry comprising: nine fuse-added elements,which receive address lines externally by one-to-one and respectivelygenerates an output signal; three enable fuse elements, programmedaccording to a fuse set enable signal so as to respectively generate aline enable signal to generate a line enable signal to enable a linedefect memory, a sector enable signal to generate a sector enable signalto enable a sector defect memory and an MAT enable signal to generate anMAT enable signal to enable an MAT defect memory; a first NAND gatehaving three inputs and an output, the three inputs respectivelyreceiving the three bottom output signals of the nine fuse-addedelements, and generating an output signal from the output; a second NANDgate having three inputs and an output, the three inputs respectivelyreceiving the three middle output signals of the nine fuse-addedelements, and generating an output signal from the output; a third NANDgate having three inputs and an output, the three inputs respectivelyreceiving the three top output signals of the nine fuse-added elements,and generating an output signal from the output; a first NOR gate havingthree inputs and an output, the three inputs respectively receiving theoutput signals from the first NAND gate, the second NAND gate and thethird NAND gate, and generating an output signal from the output; afirst NOR gate having two inputs and an output, the two inputsrespectively receiving the output signals from the second NAND gate andthe third NAND gate, and generating an output signal from the output; aninverter, which receives an output signal of the third NAND gate andgenerates an inverted phase output signal; a fourth NAND gate having twoinputs and an output, the two inputs respectively receiving the lineenable signal and the output signal of the first NOR gate, andgenerating a line replacement signal from the output; a fifth NAND gatehaving two inputs and an output, the two inputs respectively receivingthe sector enable signal and the output signal of the second NOR gate,and generating a sector replacement signal from the output; a sixth NANDgate having two inputs and an output, the two inputs respectivelyreceiving the MAT enable signal and the inverted phase output signal,and generating an MAT replacement signal from the output.
 14. Theadaptable redundancy circuitry of claim 13, wherein the line defectmemory is column defect memory.
 15. The adaptable redundancy circuitryof claim 13, wherein the line defect memory is row defect memory.